PBRVITS (AUTONOMOUS),Kavali.
21A050309 MPMC_II CSE
OPERATING MODES OF 8259A PIC:
The different modes of operation of 8259A can be programmed by setting or
resting the appropriate bits of the ICW or OCW.
The different modes of operation of 8259A are explained in the following.
FULLY NESTED MODE: This is the default mode of operation of 8259A. IR0 has the highest
priority and IR7 has the lowest one. When interrupt request are noticed, the highest
priority request amongst them is determined and the vector is placed on the data bus.
The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI
command just before returning from the service routine or the AEOI bit is set.
END OF INTERRUPT (EOI):
The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command, issued
before returning from the interrupt service routine. There are two types of EOI
commands specific and non-specific.
AUTOMATIC ROTATION:
This is used in the applications where all the interrupting devices are of equal
priority. In this mode, an interrupt request IR level receives priority after it is served
while the next device to be served gets the highest priority in sequence. Once all the
device are served like this, the first device again receives highest priority.
AUTOMATIC EOI MODE:
Till AEOI=1 in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A
performs a non-specific EOI operation at the trailing edge of the last INTA pulse
automatically. This mode should be used only when a nested multilevel interrupt
structure is not required with a single 8259A.
SPECIFIC ROTATION:
In this mode a bottom priority level can be selected, using L2, L1 and L0 in OCW2
and R=1, SL=1, EOI=0. The selected bottom priority fixes other priorities. If IR5 is
selected as a bottom priority, then IR5 will have least priority and IR4 will have a next
higher priority. Thus IR6 will have the highest priority.
SPECIFIC MASK MODE:
In specific mask mode, when a mask bit is set in OCW1, it inhibits further
interrupts at that level and enables interrupt from other levels, which are not masked.
BUFFERED MODE:
When the 83259A is used in the systems where bus driving buffers are used on
data buses. The problem of enabling the buffers exists. The 8259A sends buffer enable
signal on 𝑆𝑃 / 𝐸𝑁 pin, whenever data is placed on the bus.
CASCADE MODE:
The 8259A can be connected in a system containing one master and eight slaves
(maximum) to handle upto 64 priority levels. The master controls the slaves using CAS0-
CAS2 which act as chip select inputs (encoded) for slaves.
PROGRAMMING THE 8259A PIC:
The 8259A accepts two types of command words generated by the microprocessor.
1. Initialization Command Words (ICWs)
2. Operation Command Words (OCWs)